This application relies for priority upon Korean Patent Application No. 99-19984, filed on Jun. 1, 1999, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to a semiconductor memory device. More particularly, the present invention relates to a refresh control circuit for controlling a refresh cycle that performs the refresh of memory cell data and to a related refreshing method.
Semiconductor memory devices can be generally divided into two groups; dynamic RAM (DRAM) devices and static RAM (SRAM) devices. In an SRAM, a memory cell is often realized by four transistors that constitute a latch. Stored data of such a memory cell is preserved without being damaged unless the power supply is removed. As a result, an SRAM does not require a refresh operation for re-charging the memory cell data during its use.
In contrast, in a DRAM, a memory cell is often made of a single transistor and a single capacitor, with the memory cell data being stored in the capacitor. Since the capacitor is fabricated on a semiconductor substrate and is not completely electrically isolated from its surroundings, leakage current may occur around the capacitor, thus damaging the data stored in the capacitor of the memory cell. As a result, a refresh operation is necessary in a DRAM to periodically re-charge the data in the memory cell.
Such a refresh operation is generally performed according to the following process. Initially, one or more word lines are sequentially selected. The data stored in the capacitors of the memory cells coupled to the selected word lines are amplified by a sense amplifier and are then restored once more to their respective storage capacitors.
The stored data in the memory cells are thus preserved without being damaged through this refresh process. To continually preserve the stored data, the refresh process must be performed at predetermined intervals referred to as refresh cycles.
A conventional refresh cycle is designated by refresh requests from an external processor. The timing of the refresh cycle is determined by a counter included in an oscillator. The counter generates division signals having division rates that are power of two multiples, i.e., xc3x972, xc3x974, xc3x978, xc3x9716, . . . , of a clock cycle by dividing the clock signals of the oscillator.
The refresh cycle is then determined by selecting one of the division signals depending upon the characteristic of a DRAM cell and a chip architecture. For example, assume that the refresh is performed in a refresh cycle of 8xcex with respect to the clock cycle xcex of the oscillator. If the length of the refresh cycle must be increased based upon the characteristic of the DRAM cell, the refresh cycle will be changed to 16xcex. When the length of a refresh cycle must be increased, only 16xcex, which is a multiple of 8xcex, can be selected since it is not possible to select a refresh cycle between 8xcex and 16xcex.
Therefore, a more flexible refresh control circuit would be desirable. Such a circuit would make it possible to finely control a change in the refresh cycle so as to select a cycle of any number, i.e., xc3x971, xc3x972, xc3x973, xc3x974, . . . , rather than a cycle which is a power of two multiple, i.e., xc3x972, xc3x974, xc3x978, xc3x9716, . . . , of the clock cycle of the oscillator in selecting the refresh cycles.
To solve the above problem, it is an object of the present invention to provide a counter circuit capable of controlling division rates with respect to a clock signal and a refresh control circuit to control a change in refresh cycles by employing the counter circuit.
It is another object of the present invention to provide a refreshing method of such a refresh control circuit.
Accordingly, to achieve the first object, a counter circuit is provided for receiving a clock signal and generating a counter signal having a predetermined division rate with respect to the clock signal. The counter circuit comprises a divider for dividing the clock signal and generating a plurality of division signals, a register for selecting the division rate, and a counter signal generator for receiving the division signals and generating the counter signal when one of the division signals matches a division value stored in the register. The division value preferably indicates the division rate.
The register preferably comprises a plurality of fuses, and the division rate is determined by detecting whether the fuses are on or off.
The counter circuit further may comprise a counter reset circuit for suppressing the operation of the divider and initializing the operation of the divider.
The division signals preferably correspond to integral multiples of the clock signal, and more preferably correspond to times-two multiples of the clock signal.
A refresh control circuit is also provided for controlling refresh cycles so as to refresh data stored in memory cells. The refresh control circuit comprises a refresh counter for generating a plurality of frequency division signals by dividing a clock signal in response to a refresh signal for directing a refresh operation, and a refresh activation signal generator for generating a refresh activation signal corresponding to the refresh cycle according to values stored in a register.
The refresh activation signal generator may further comprise a plurality of fuses formed in the register, the values stored in the register being determined by detecting whether the fuses are on or off.
The refresh activation signal is preferably generated while the frequency division signals are equal to values stored in the register.
The frequency division signals preferably correspond to integral multiples of the clock signal, and more preferably correspond to times-two multiples of the clock signal.
The refresh circuit may further comprise a refresh resetting unit for suppressing the operation of the refresh counter and initializing the refresh counter.
To achieve the second object, a method is provided for refreshing data stored in memory cells. The method comprises (a) generating a refresh signal for directing the refresh operation, (b) activating a refresh counter for generating a plurality of frequency division signals having predetermined division rates with respect to a clock signal in response to the refresh signal, (c) generating a refresh activation signal while the frequency division signals are equal to division values stored in a register, and (d) initializing the refresh counter by generating a refresh reset signal having a predetermined pulse width in response to the refresh activation signal. The refresh operation is performed by a refresh activation signal having a refresh cycle by repeating steps (a) through (d).
The division values stored in the register are preferably determined by detecting whether each of a plurality of fuses in the register are on or off.
According to the present invention, there are a wider variety of refresh cycles available, since the refresh cycle is determined by the values stored in the register.